The present disclosure relates generally to semiconductor device modeling and manufacturing, and more particularly to the methods for correlating transistor models to the fabricated features of the device transistors.
The production of semiconductor integrated circuits (ICs) and devices requires the use of many steps to define and fabricate specific circuit components and circuit layouts onto an underlying substrate. These steps include design processes (function design, logic design, physical/layout designs and the like), manufacturing processes (material, device fabrication and the like) and test processes (device physical, electrical, functionality testing and the like). The design processes include modeling methods by which certain physical dimensional aspects of the device's transistors are correlated to certain electrical parametric performances of the transistors. Such transistor models are used to help extract and define the initial manufacturing fabrication parameters, as well as for determining changes and re-targets to the fabricated transistor physical dimensional features to re-center their electrical parametric performances.
Device circuits utilizing field-effect transistors (FETs) are commonly modeled to determine the transistors' gate poly-silicon electrode length, the dimensional length of the physical channel between the transistors' source and drain regions. The OD area width, the transistors' electrically active region under the gate poly-silicon electrode, is also a modeled parameter that correlates strongly to device transistor performance. It is important from the view of the device designers and for the manufacturing operations, that the extraction models for transistor gate length and OD area width reliably and accurately predict and represent the electrical characteristics of the transistors.
Typical transistor models, such as the SPICE model for example, translate the modeled (drawn) gate length and OD area width parameters to the actual physically measured dimensions for the fabricated transistors. Such models correct or correlate the modeled, drawn gate poly-silicon length and area width dimensions to the actual fabricated transistor CD (critical dimension) values by either a fixed CD offset modification, or by a differently specified offset value applied to the in-line fabrication operations. These transistor models extract corrected transistor physical dimensional parameters that are usually optimized for a specific device transistor layout style and pattern. In actuality, due to certain real-life process issues, the transistor models are often not optimal for all varieties of device transistor layout styles and patterns. As example, for the advanced device process technologies with gate lengths of less than 65 nm (nano-meter) and OD area widths around 110 nm, certain systematic process phenomena and issues may induce as much as and larger than 10% drifts to the final electrical performance parameters of the transistors. As a result, the transistor models experience non-modeled inaccuracies and additional offset errors between the actual fabricated device transistors and the expected electrical performance characteristics of the same. Such inaccuracies and errors may occur not only between one product device to another, but also between different operating circuits within a given device. As device transistor dimensional geometries shrink with the more advanced device and process technology generations, the issues and difficulties for maintaining reliable and accurate transistor models become more important for maintaining device performance and high production/device yields.
The flow diagram 100 of FIG. 1 illustrates a method for correcting and correlating the transistor gate length and OD area width parameters to the transistor electrical performance parameters. Both flows require the use of collected data, the in-line measured transistor CD data from the transistors during fabrication and the measured electrical performance data taken from the fabricated transistors. The in-line CD data collection is shown as step 102 of both flow diagrams. The collection of transistor electrical data is shown as the next step 104 of both flow diagrams. In FIG. 1, in the next step 106, the collected in-line CD and final transistor electrical data are used to calculate and determine correction, offset factors to be applied within the transistor model such that the corrected, offset CD parameters of the model match that of the measured in-line CD data. The new correction, offset factors are then applied to the transistor model, shown as step 108 of FIG. 1. The transistor model is subsequently used for extraction of electrical performance for device transistors with a variety of layouts.
Accordingly, it is desirable to have an improved method for modeling transistors such that the physical parameters of the transistor features are correlated well to the electrical performance of the same.